The present invention relates to a semiconductor memory device, and more particularly to a technique which can be effectively utilized in a data input circuit in a synchronous dynamic type random access memory (RAM) of a double data rate (DDR) configuration.
According to the specifications of the data input system in a double data rate synchronous dynamic random access memory (DDR SDRAM), write data are entered in synchronism with an edge of a data strobe signal DQS as illustrated in FIG. 8, not with a clock signal for controlling the timing of the whole SDRAM. In other words, when a write command (WRITE) is entered at the rise timing of the clock signal CLK, the DQS once shifts from a high impedance state to a low level for a period tWPRE (PREAMBLE).
After that, a data strobe signal DQS which varies from a clock CLK matching the write command from a low level to a high level at a timing defined by a time length tDQSS is entered and, in response to the variations of this signal DSQ from the low level to the high level and from the high level to the low level, input data D0 through D4 and the like, whose set-up/hold time (tQDQSS/tQDQSH) is secured, are entered. The time length tDQSS is defined in a range of 0.75 tCK to 1.25 tCK. Upon entry of input data equivalent to a desired data length (D0 through D3 in the chart), the clock signal DQS takes on a low level (POSTAMBLE) during a time length tWPST, and again returns to a high impedance state.
Before this invention, the present inventors had developed an input circuit matching the specifications of the aforementioned data input system, as illustrated in FIG. 9. In this circuit, a three-stage shift register and a two stage shift register are configured by combining through-latch circuits operated by the clock signal DQS, wherein the data D0 and D2 are transferred by the three-stage shift register in synchronism with the rising edge of the clock signal DQS, while the data D1 and D3 are transferred by the two-stage shift register in synchronism with the falling edge of the clock signal DQS, converted in parallel into two sequences of input data, DIN1 and DIN2, and entered into a pair of latch circuits which take in input signals with a clock signal CLK to change the timing between DQS and CLK, and a selected memory cell in a memory array is cause to make a write action in synchronism with this clock signal CLK.
However, this input circuit was found to entail the following problem. Thus, as shown in FIG. 10, if the time length tDQSS defined by the clock CLK matching the write command is as short as 0.75 tCK, when data equivalent to a desired data are entered, the clock signal DQS returns to a high impedance state before a clock signal DCLK formed in synchronism with the clock signal CLK arrives, and noise known as glitch may arise in an output circuit generating the clock signal DQS when an input terminal into which the clock signal DQS is inputted returns to the high impedance state. The input circuit would mistake this noise for the clock signal DQS and generate a shift clock, which causes the shift registers to perform a one-bit shifting action. This has been found to give rise to a problem that this shifting action crosses out the data which should be held, and invalid data (INVALID) are taken in as write data at the timing of a clock signal DICLK, which is mounted with a time lag.
An object of the present invention is to provide a semiconductor memory device for enhanced DQS-glitch immunity. Another object of the invention is to semiconductor memory device of a DDR configuration, which is more convenient to use.
Typical ones of the aspects of the invention disclosed in this application will be described below. According to one aspect of the invention, there is provided a dynamic type random access memory (RAM) the operation of whose internal circuits is controlled in synchronism with a clock signal, provided with an input circuit which, using a second clock signal entered when in a write operation, successively takes a plurality of sets of write data serially entered matching the second clock signal into a plurality of first latch circuits, and takes the write data taken into the first latch circuits into a second latch circuit by using the second clock signal to convey them into an input/output data bus, wherein a logic circuit is provided for masking any noise arising at the end of the second clock signal according the logic of the first clock signal and the second clock signal to generate a third clock signal, which is supplied to a first latch circuit for outputting the write data to at least the input of the second latch circuit.